A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The conventional scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension implant 104 and a source extension implant 106. The drain extension implant 104 and the source extension implant 106 are shallow junction implants to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 which is comprised typically of silicon dioxide (SiO.sub.2), and a gate structure 118 which is typically a polysilicon gate. A gate silicide 120 is formed on the polysilicon gate 118 for providing contact to the polysilicon gate 118. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the polysilicon gate 118 and the gate oxide 116. When the spacer 122 is comprised of silicon nitride (SiN), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the polysilicon gate 118 and the gate oxide 116. The spacer 122 covers the separation of the drain extension implant 104 and the drain contact junction 108, and the separation of the source extension implant 106 and the source contact junction 112.
Referring to FIG. 2, in the MOSFET 100 of the prior art, when the width 126 of the spacer 122 is narrow, the deeper drain contact junction 108 and the deeper source contact junction 112 are closer to the channel region 128 of the MOSFET 100 resulting in a punch-through effect in the channel region 128, as known to one of ordinary skill in the art of integrated circuit fabrication. Such a punch-through effect may disadvantageously cause excessive leakage current through the MOSFET 100. (Elements having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function.)
On the other hand, referring to FIG. 3, in the MOSFET 100 of the prior art, when the width 126 of the spacer 122 is wide, the drain contact junction 108 and the source contact junction 112 are further apart, but the series resistance at the drain and the source of the MOSFET 100 is larger, as known to one of ordinary skill in the art of integrated circuit fabrication. Such a larger resistance degrades the drive current through the MOSFET 100 and thus degrades the speed performance of the MOSFET 100. (Elements having the same reference number in FIGS. 1, 2, and 3 refer to elements having similar structure and function.)
Because of these disadvantages of the drain contact junction 108 and the source contact junction 112 of the prior art, elevated drain and source contact structures are used to replace the drain contact junction 108 and the source contact junction 112, as known to one of ordinary skill in the art of integrated circuit fabrication. Referring to FIG. 4, for fabrication of the elevated drain and source contact structures in the prior art, a gate dielectric 202 which is comprised typically of silicon dioxide (SiO.sub.2), and a gate structure 204 which is typically a polysilicon gate is formed on the surface of the semiconductor substrate 102. A drain extension implant 206 and a source extension implant 208 are then formed in the semiconductor substrate 102 to have a relatively large area such that elevated drain and source contact structures may be selectively grown thereon.
Referring to FIGS. 4 and 5, a first spacer 210 is formed on the sidewalls of the gate structure 204 and the gate dielectric 202. (Elements having the same reference number in FIGS. 4 and 5 refer to elements having similar structure and function.) The first spacer 210 is typically comprised of silicon nitride (SiN), and in that case, a spacer liner oxide 212 is deposited as a buffer layer between the first spacer 210 and the sidewalls of the gate structure 204 and the gate dielectric 202, and between the first spacer 210 and the surface of the drain extension implant 206 and the source extension implant 208, as illustrated in FIG. 5.
Referring to FIG. 6, an elevated drain contact structure 214 is grown onto the exposed portions of the drain extension implant 206 typically by selective epitaxial growth when the elevated drain contact structure 214 is comprised of silicon. Similarly, an elevated source contact structure 216 is grown onto the exposed portions of the source extension implant 208 typically by selective epitaxial growth when the elevated source contact structure 216 is comprised of silicon.
Referring to FIG. 6, during the selective epitaxial growth of the elevated drain contact structure 214, a drain facetted surface 218 forms on the elevated drain contact structure 214 due to the crystalline structure of the elevated drain contact structure 214. (Elements having the same reference number in FIGS. 4, 5, and 6 refer to elements having similar structure and function.) The drain facetted surface 218 faces toward the first spacer 210 on the sidewall of the gate structure 204. Similarly, a source facetted surface 220 forms on the elevated source contact structure 216 due to the crystalline structure of the elevated source contact structure 216. The source facetted surface 220 faces toward the first spacer 210 on the sidewall of the gate structure 204.
After formation of the elevated drain contact structure 214 and the elevated source contact structure 216, dopants are implanted and activated into the elevated drain contact structure 214 and the elevated source contact structure 216, as known to one of ordinary skill in the art of integrated circuit fabrication. Then, silicide is formed on the elevated drain contact structure 214 and the elevated source contact structure 216, as known to one of ordinary skill in the art of integrated circuit fabrication.
However, unfortunately in the prior art, when dopant is implanted and activated into the drain facetted surface 218 and the source facetted surface 220, such dopant may reach down into the semiconductor substrate creating locally deep junctions since the elevated drain contact structure 214 and the elevated source contact structure 216 are thinner at the drain facetted surface 218 and the source facetted surface 220. Such locally deep junctions under the drain facetted surface 218 and the source facetted surface 220 disadvantageously alter the drain extension implant 206 and the source extension implant 208 which are designed to be especially shallow in scaled down MOSFETs to prevent short-channel effects. Thus, locally deep junctions under the drain facetted surface 218 and the source facetted surface 220 cause recurrence of short-channel effects in the MOSFET of the prior art.
In addition, silicide formed on the drain facetted surface 218 and the source facetted surface 220 would be closer to the drain extension implant 206 and the source extension implant 208 since the elevated drain contact structure 214 and the elevated source contact structure 216 are thinner at the drain facetted surface 218 and the source facetted surface 220. Such a close location of the silicide at the drain facetted surface 218 and the source facetted surface 220 to the drain extension implant 206 and the source extension implant 208 respectively results in severe junction leakage current through the drain extension implant 206 and the source extension implant 208.
Despite these disadvantages, elevated drain and source contact structures are desired for further scaling down MOSFETs to submicron and nanometer dimensions. Thus, a process is desired for fabricating a MOSFET having the elevated drain and source contact structures with prevention of dopant implant and silicide formation at the drain facetted surface 218 and the source facetted surface 220.
Furthermore, referring to FIG. 6, during the selective epitaxial growth of the elevated drain contact structure 214 and the elevated source contact structure 216, a mushroom cap 222 may form on top of the gate structure 204 which may be comprised of polysilicon. A process is desired for effectively preventing the gate structure 204 from turning into such a mushroom shape.